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| PD - 95825A AUTOMOTIVE MOSFET IRLR024Z IRLU024Z HEXFET(R) Power MOSFET D Features n n n n n n Logic Level Advanced Process Technology Ultra Low On-Resistance 175C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax VDSS = 55V G S RDS(on) = 58m ID = 16A Description Specifically designed for Automotive applications, this HEXFET(R) Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. D-Pak IRLR024Z I-Pak IRLU024Z Absolute Maximum Ratings Parameter ID @ TC = 25C Continuous Drain Current, VGS @ 10V (Silicon Limited) ID @ TC = 100C Continuous Drain Current, VGS @ 10V IDM Pulsed Drain Current Max. 16 11 64 35 0.23 16 25 25 See Fig.12a, 12b, 15, 16 -55 to + 175 Units A W W/C V mJ A mJ C PD @TC = 25C Power Dissipation Linear Derating Factor Gate-to-Source Voltage VGS EAS (Thermally limited) Single Pulse Avalanche Energyd EAS (Tested ) Single Pulse Avalanche Energy Tested Value IAR EAR TJ TSTG Avalanche CurrentA Repetitive Avalanche Energy Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds h g 300 (1.6mm from case ) Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient Typ. Max. 4.28 40 110 Units C/W i --- --- --- HEXFET(R) is a registered trademark of International Rectifier. www.irf.com 1 06/21/04 IRLR/U024Z Electrical Characteristics @ TJ = 25C (unless otherwise specified) Parameter V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Coss Coss Coss eff. Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. Typ. Max. Units 55 --- --- --- --- 1.0 7.4 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.053 46 --- --- --- --- --- --- --- --- 6.6 1.6 3.9 8.2 43 19 16 4.5 7.5 380 62 39 180 50 81 --- --- 58 80 100 3.0 --- 20 250 200 -200 9.9 --- --- --- --- --- --- --- nH --- --- --- --- --- --- --- pF ns nC nA V S A m V Conditions VGS = 0V, ID = 250A VGS = 10V, ID = 9.6A VGS = 4.5V, ID V/C Reference to 25C, ID = 1mA VGS = 5.0V, ID = 5.0A e e = 3.0A e VDS = VGS, ID = 250A VDS = 25V, ID = 9.6A VDS = 55V, VGS = 0V VDS = 55V, VGS = 0V, TJ = 125C VGS = 16V VGS = -16V ID = 5.0A VDS = 44V VGS = 5.0V VDD = 28V ID = 5.0A RG = 28 VGS = 5.0V e e D G S Between lead, 6mm (0.25in.) from package and center of die contact VGS = 0V VDS = 25V = 1.0MHz VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 44V, = 1.0MHz VGS = 0V, VDS = 0V to 44V f Source-Drain Ratings and Characteristics Parameter IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- --- --- --- --- 16 11 16 A 64 1.3 24 17 V ns nC Conditions MOSFET symbol showing the integral reverse G S D p-n junction diode. TJ = 25C, IS = 9.6A, VGS = 0V TJ = 25C, IF = 9.6A, VDD = 28V di/dt = 100A/s e e Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) 2 www.irf.com IRLR/U024Z 100 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V 100 TOP VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V 3.0V ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 10 BOTTOM 10 BOTTOM 3.0V 1 1 3.0V 60s PULSE WIDTH Tj = 25C 0.1 0.1 1 V DS, Drain-to-Source Voltage (V) 10 60s PULSE WIDTH Tj = 175C 0.1 0.1 1 V DS, Drain-to-Source Voltage (V) 10 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 Gfs, Forward Transconductance (S) 15 ID, Drain-to-Source Current () T J = 175C 10 T J = 25C 10 TJ = 175C 1 T J = 25C VDS = 10V 60s PULSE WIDTH 0.1 0 2 4 6 8 10 12 5 V DS = 8.0V 300s PULSE WIDTH 0 0 2 4 6 8 10 12 14 16 ID,Drain-to-Source Current (A) VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3 IRLR/U024Z 10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 6.0 ID= 5.0A VGS , Gate-to-Source Voltage (V) 5.0 VDS= 44V VDS= 28V VDS= 11V C, Capacitance(pF) 1000 4.0 Ciss Coss Crss 3.0 100 2.0 1.0 10 1 10 100 0.0 0 1 2 3 4 5 6 7 VDS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nC) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 100 1000 OPERATION IN THIS AREA LIMITED BY R DS(on) T J = 175C 10 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 100 10 100sec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10 1msec 10msec 100 1000 T J = 25C VGS = 0V 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U024Z 16 RDS(on) , Drain-to-Source On Resistance 2.5 14 12 10 8 6 4 2 0 25 50 75 100 125 150 175 T C , Case Temperature (C) ID = 5.0A VGS = 5.0V 2.0 ID, Drain Current (A) (Normalized) 1.5 1.0 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Normalized On-Resistance vs. Temperature 10 D = 0.50 Thermal Response ( Z thJC ) 1 0.20 0.10 0.05 0.1 0.02 0.01 J R1 R1 J 1 2 R2 R2 C Ri (C/W) i (sec) 2.354 0.000354 1.926 0.001779 1 2 0.01 SINGLE PULSE ( THERMAL RESPONSE ) Ci= i/Ri Ci= i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 0.001 1E-006 1E-005 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U024Z EAS , Single Pulse Avalanche Energy (mJ) 15V 100 VDS L DRIVER 80 ID 1.2A 1.8A BOTTOM 9.6A TOP RG 20V VGS D.U.T IAS tp + V - DD 60 A 0.01 40 Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) I AS Fig 12b. Unclamped Inductive Waveforms QG Fig 12c. Maximum Avalanche Energy vs. Drain Current 10 V QGS VG QGD VGS(th) Gate threshold Voltage (V) 2.5 2.0 Charge Fig 13a. Basic Gate Charge Waveform ID = 250A 1.5 L DUT 0 VCC 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 1K T J , Temperature ( C ) Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature 6 www.irf.com IRLR/U024Z 100 Avalanche Current (A) 10 Duty Cycle = Single Pulse 0.01 0.05 Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses 1 0.10 0.1 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 15. Typical Avalanche Current vs.Pulsewidth 30 EAR , Avalanche Energy (mJ) 25 TOP Single Pulse BOTTOM 1% Duty Cycle ID = 9.6A 20 15 10 5 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Notes on Repetitive Avalanche Curves , Figures 15, 16: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 12a, 12b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 15, 16). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav Fig 16. Maximum Avalanche Energy vs. Temperature www.irf.com 7 IRLR/U024Z Driver Gate Drive D.U.T + P.W. Period D= P.W. Period VGS=10V + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD VDD + - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs RD V DS VGS RG 10V Pulse Width 1 s Duty Factor 0.1 % D.U.T. + -VDD Fig 18a. Switching Time Test Circuit VDS 90% 10% VGS td(on) tr t d(off) tf Fig 18b. Switching Time Waveforms 8 www.irf.com IRLR/U024Z D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB 0.58 (.023) 0.46 (.018) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) -B1.52 (.060) 1.15 (.045) 2.28 (.090) 4.57 (.180) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN T HE AS SEMBLY LINE "A" Note: "P" in ass embly line pos ition indicates "Lead-Free" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFR120 916A 12 34 ASS EMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFR120 12 P916A 34 ASS EMBLY LOT CODE DAT E CODE P = DESIGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS SEMBLY S IT E CODE www.irf.com 9 IRLR/U024Z I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3X 1.14 (.045) 0.76 (.030) 3X 0.89 (.035) 0.64 (.025) M AMB 1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018) 2.28 (.090) 2X 0.25 (.010) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WIT H ASSEMBLY LOT CODE 5678 AS SEMBLED ON WW 19, 1999 IN T HE ASSEMBLY LINE "A" Note: "P" in as sembly line position indicates "Lead-Free" INTERNATIONAL RECT IFIER LOGO PART NUMBER IRFU120 919A 56 78 AS SEMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 19 LINE A OR PART NUMBER INTERNAT IONAL RECTIF IER LOGO IRF U120 56 78 ASS EMBLY LOT CODE DATE CODE P = DES IGNAT ES LEAD-F REE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS SEMBLY S IT E CODE 10 www.irf.com IRLR/U024Z D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Limited by TJmax, starting TJ = 25C, L = 0.54mH RG = 25, IAS = 9.6A, VGS =10V. Part not recommended for use above this value. Pulse width 1.0ms; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Notes: Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance. This value determined from sample failure population. 100% tested to this value in production. When mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994. RismeasuredatTJofapproximately90C. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/04 www.irf.com 11 |
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